Cache modules are high-speed memories that facilitate fast retrieval of information including data and instructions. Typically, cache modules are relatively expensive and are characterized by a small size, especially in comparison to high-level memory modules.
The performance of modern processor-based systems usually depends upon the performance of the cache module and especially to a relationship between cache module hits and cache module misses.
Various cache module modules and processor architectures, as well as data retrieval schemes, were developed over the years, to meet increasing performance demands. These architectures included multi-port cache modules, multi-level cache module architecture, super scalar type processors and the like.
Processors are capable of requesting information from a cache module and, alternatively or additionally, from another memory module that can be a high-level memory module. The high-level memory module can also be a cache module memory, another internal memory and even an external memory.
There are various manners to write information into a cache module or a high-level memory module. Write-back involves writing one or more information units to the cache module. The cache module sends one or more information units to the high-level memory once that one or more information units are removed from the cache module. The latter operation is also known in the art as flushing the cache modules. Write-back allocate involves writing the information unit to the cache only if the address of the information unit is present in the cache. If it is not present then the processor can be stalled until the entire cache line that includes that address of the information unit is fetched.
The cache module includes multiple lines that in turn are partitioned to segments. Each segment is associated with a validity bit and a dirty bit. A valid bit indicates whether a certain segment includes valid information. The dirty bit indicates if the segment includes a valid information unit that was previously updated but not sent to the high-level memory module. If a write back policy is implemented only the segments that are associated with an asserted dirty bit are written to the high-level memory module.
There is a need to provide an efficient method and apparatus for fetching information to a cache module.